This invention broadly relates to an error bit correcting method and an error bit correcting circuit for correcting an error bit of a data signal inputted via a radio channel for a time division multiple access (TDMA) system in a mobile communication system.
In particular, this invention relates to an error bit correcting method and an error bit correcting circuit which are capable of improving a line quality by improving an accuracy of an error correction when an error bit of a BCH (Bose-Chaudhari-Hocquenghem)-coded data signal is corrected by the use of a predetermined error correcting code.
In general, a data signal propagated via a radio channel often includes error bits such that the data signal is changed into an error data signal in comparison with a wire-channel communication system in a mobile communication system.
To this end, a BCH (Bose-Chaudhari-Hocquenghem) code is generally used in the propagated data signal. Herein, the BCH code is a typical cyclic code, and can comply with various error correcting abilities and code lengths.
Under this circumstance, the data signal is transmitted via an interleave so that an error correcting code (ECC) effectively serves.
Conventionally, the propagated BCH-coded data signal has been attached with a character (namely, a CRC character) for detecting an error for a single data signal at a transmitting side on the basis of a CRC (cyclic redundancy check code) system.
Further, the predetermined BCH error correcting code (hereinafter, referred to as a CK code) is inserted for each data line (series) during an interleaving process to constitute one block so as to correct an error bit at a receiving side.
More specifically, the BCH code error correction is first carried out at the receiving side. In this event, a bit correction is performed for one bit position calculated by the CK code at every data line.
Accordingly, the correction can be carried out in the case where the number of error bits is equal to one. However, the correction can not be performed when the number of error bits is two bits or more.
Further, after the error of the BCH code is corrected for each line, the error is detected by performing the CRC process for an entire block data.
In consequence, when the bit is not corrected by the BCH code error correction, a CRC error takes place by CRC error detection. As a result, this block data signal is discarded or removed.
Herein, this conventional operation will be explained with reference to FIGS. 1A and 1B.
For example, when an error code exists at a bit position D12 in a data line 101 after de-interleave as illustrated in FIG. 1A, the bit position D12 is calculated from the CK code and the data bit included in the line data 101.
Thereafter, the bit at the bit position D12 is reversed or turned over as indicated in an error bit position information 102.
Thereby, the error is corrected, and a flag is placed or arranged at a bit position D1. Thus, where only one error bit exists for each data line, a CRC calculated result after the error correction is conducted for all lines indicates xe2x80x9cCRC error absencexe2x80x9d.
On the other hand, when the error codes exist at two bit positions D6 and D15 in a data line 111 after the de-interleaving as illustrated in FIG. 1B, a bit position D11 placed at an approximately intermediate portion between the two bit positions is calculated from the CK code and the data bit included in the data line 111 in the BCH code error correction.
Consequently, the bit positioned at the bit position D11 is reversed or turned over as indicated in an error bit position information 112, and a flag is arranged at a bit position D1. In this case, a final CRC calculated result represents xe2x80x9cCRC error presencexe2x80x9d because the error bit still remains.
When the line data includes two or more error bits in the above-mentioned time division multiple access system, the CRC calculated result inevitably represents xe2x80x9cCRC error presencexe2x80x9d. In consequently, all block data signals are discarded or removed. As a result, the line quality is degraded.
This reason will be explained as follows.
Namely, when the data line includes only one error bit after the de-interleaving, the error can be accurately corrected.
By contrast, the data line includes two or more error bits, the error bit can not be accurately specified. In consequence, the error bit can not be corrected.
It is therefore an object of this invention to provide an error bit correcting method and an error bit correcting circuit which are capable of accurately correcting two or more error bits with respect to a BCH code error correction in a time division multiple access system.
In a correcting method according to this invention, error bits of a data signal inputted via a radio channel are corrected in a time division multiple access system.
First, at least one of a RSSI (radio signal strength indicator) information and a phase error information is determined at every symbol when the data signal is received.
Subsequently, it is judged whether or not the determined information falls within a range of a predetermined value indicating deterioration of a line quality.
Consequently, one bit outside the range is determined as an error bit.
Finally, the error bit is reversed.
Further, a BCH (Bose-Chaudhari-Hocquenghem) code error correction may be used in addition. In this event, a predetermined BCH error correction code is used for a BCH coded data signal in the BCH code error correction.
The BCH code error correction is carried out by using the predetermined error correction code after the bit correction is performed by determining the one bit outside the range as the error bit.
In a correcting method according to this invention, error bits of a BCH coded data signal are corrected in a time division multiple access system.
First, at least one of a RSSI information and a phase error information is determined at every symbol when the data signal is received.
Subsequently, an error of a BCH code is corrected by using a predetermined error correction code.
Next, the determined information is checked when a CRC (cyclic redundancy check code) error is detected in a predetermined CRC error detection.
Successively, it is judged whether or not the determined information falls within a range of a predetermined value indicating deterioration of a line quality.
In consequence, one bit outside the range is determined as an error bit.
Next, the error bit is reversed.
Finally, another error of the BCH code is corrected by using the predetermined error correction code.
In a correcting circuit, error bits of a data signal inputted via a radio channel are corrected in a time division multiple access system.
An information collecting portion determines a line quality at every symbol by using at least one of a RSSI information and a phase error information when the data signal is received.
An estimate bit correction portion judges whether or not the determined information falls within a range of a predetermined value indicating deterioration of the line quality, and determines one bit outside the range as an error bit, and reverses the error bit.
Further, a BCH error correction portion may correct an error of a BCH code by using a predetermined BCH error correction code for a BCH coded data signal.
With such a structure, the BCH error correction portion is given with a bit-corrected data signal by the estimate bit correction portion.
In a correcting circuit according to this invention, error bits of a BCH coded data signal are corrected in a time division multiple access system.
A BCH error correction portion corrects an error of a BCH code by using a predetermined error correction code.
An information collecting portion determines a line quality at every symbol using at least one of a RSSI information and a phase error information when the data signal is received.
An estimate bit correction portion judges whether or not the determined information falls within a range of a predetermined value indicating deterioration of the line quality, and determines one bit outside the range as an error bit, and reverses the error bit.
With this structure, the estimation bit correction portion supplies the corrected data signal into the BCH error correction portion.
As described above, when the error bits of the BCH coded data signal are corrected by using the predetermined BCH error correction code, the accuracy of the error correction is enhanced. In consequence, the line quality can be improved. This reason will be explained as follows.
It is assumed that one bit is outside the range of the predetermined value indicating the deterioration of the communication quality on the basis of at least one of the RSSI information and the phase error information with respect to the communication quality at every symbol obtained during receiving the data signal. This one bit is determined as the error bit, and is reversed. Thereby, the one bit error is corrected.
Successively, the error correction of one code is executed by using the predetermined BCH error correction code for the BCH coded data signal.
Consequently, two or more of error bits in the data line (series) formed by de-interleaving in the BCH coded data signal can be accurately corrected.
Conventionally, the block data signal having the data line including two or more of error bits has been discarded or removed.
By contrast, such error correction will become possible, and many data signals, which were discarded in conventional case, can be effectively utilized according to this invention.